Error: SERDES DPA Block node 'lvds_rx:lvds_rx_inst0|altlvds_rx:ALTLVDS_RX_component|lvds_rx_lvds_rx:auto_generated|lvds_rx_dpa3' is not properly connected on the 'RXFCLK' port. It must be connected to one of the valid ports listed below. - Error: SERDES DPA Block node 'lvds_rx:lvds_rx_inst0|altlvds_rx:ALTLVDS_RX_component|lvds_rx_lvds_rx:auto_generated|lvds_rx_dpa3' is not properly connected on the 'RXFCLK' port. It must be connected to one of the valid ports listed below. Description Due to a problem in the Quartus® II software version 12.1 and later, you may see this error in Arria® V devices when using the ALTLVDS_RX mega function in external PLL mode. Error: SERDES DPA Block node 'lvds_rx:lvds_rx_inst0|altlvds_rx:ALTLVDS_RX_component|lvds_rx_lvds_rx:auto_generated|lvds_rx_dpa3' is not properly connected on the 'RXFCLK' port. It must be connected to one of the valid ports listed below. Info: Can be connected to LVDSCLK port of arriav_pll_lvds_output WYSIWYG Info: Can be connected to OUTCLK port of generic_pll WYSIWYG Resolution To workaround this problem, an LVDS buffer needs to be inserted between the external pll and the ALTLVDS instance on the rx_inclock and the rx_enable ports. Refer to the related solution below to learn how to add an intermediate LVDS buffer between the external PLL and ALTLVDS IP. Related Articles How do I insert an LVDS buffer between an Altera_PLL and ALTLVDS_RX or ALTLVDS_TX megafunction in external PLL mode for Cyclone V, Arria V, and Stratix V devices? Custom Fields values: ['novalue'] Troubleshooting 2205792132 False ['PLL'] ['FPGA Dev Tools Quartus II Software'] 12.1.1 12.1 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA'] ['novalue'] ['novalue'] ['novalue']