Why does the PLL simulation fail with Verilog HDL simulation model for Intel® Cyclone® 10 LP device? - Why does the PLL simulation fail with Verilog HDL simulation model for Intel® Cyclone® 10 LP device? Description The Verilog HDL simulation model for IOPLL IP for Intel® Cyclone® 10 LP devices is not supported in the Intel® Quartus® Prime Standard Edition software version 17.1 and earlier. You will see that the IOPLL output clocks do not toggle. Resolution To simulate the IOPLL IP for Intel® Cyclone® LP devices, either use the VHDL simulation model in 17.1 or the Verilog HDL model in the Intel® Quartus® Prime Standard Edition software version 18.0 or later. Custom Fields values: ['novalue'] Troubleshooting 1507059398 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Standard'] 18.0 17.1 ['Cyclone® 10 LP FPGA'] ['novalue'] ['novalue'] ['novalue']