Timing Violation In Half-Rate Bridge Enabled Designs - Timing Violation In Half-Rate Bridge Enabled Designs Description Timing violation occurs during TimeQuest timing analysis for designs that use the high-performance controller II architecture with the Enable Half Rate Bridge option turned on. This issue affects all designs that use the high-performance II controller architecture with the Enable Half Rate Bridge option turned on. Timing violation occurs during compilation in the TimeQuest timing analyzer. Resolution Open the altera_avalon_half_rate_bridge_constraints.sdc file in your project directory, and edit the slow_clock variable and add derive_pll_clocks . Full-rate design derive_pll_clocks set slow_clk "*|altpll_component|auto_generated|pll1|clk[1]" Half-rate design derive_pll_clocks set slow_clk "*|altpll_component|auto_generated|pll1|clk[0]" This issue will be fixed in a future version of the DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 10.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue'] - 2021-08-25