Timing analysis for Asynchronous part of design - Timing analysis for Asynchronous part of design We have a product comprising of multiple FPGAs talking to eachother via MLVDS lines based on bandwidth allocation. The data is shared across on 100MHz MLVDS lines and is asynchronous in nature. The clock is derived at the RX end of the Receiving FPGA. In this case, how do we assign the parameters for timing constraints for ex. input delays for set_input_delay, set_output_delay, set_max_skew, set_false_path for IO ports etc. as IO ports remain unconstrained. Note: Not much documentation found on this specific asynchronous design timing constraints. Atatched reference for synchronous timing constraints we're referring. Replies: Re: Timing analysis for Asynchronous part of design Thank you @ShengN_Intel for resolving this issue. I have marked this as resolved! Replies: Re: Timing analysis for Asynchronous part of design Hi @ShengN_Intel , Can we connect over call for this? We have connected earlier for cyclone V as well (Maybe you can remeber Baker hughes, cycloneV, Manish & Maitreya). I have dropped you my email on a personal message. Replies: Re: Timing analysis for Asynchronous part of design Hi, If those are asynchronous, you may set false path to the asynchronous input and output check this link https://www.intel.com/content/www/us/en/docs/programmable/683062/17-1/setting-timing-constraints-using-the.html