run AN708 on Quartus 21.3 - run AN708 on Quartus 21.3 Dear Support, I downloaded AN708_q170. try to run it in my quartus 21.3. after I update the IP. the platform designer, told me Error: top.DUT.dma_rd_master: DUT.rd_dts_slave (0x80000000..0x80001fff) overlaps emif_0.ctrl_amm_0 (0x0..0xffffffff) Error: top.mm_clock_crossing_bridge_0.m0: emif_0.ctrl_amm_0 (0x0..0xffffffff) is outside the master's address range (0x0..0xfffffff) Error: qsys-generate failed with exit code 3: 2 Errors, 5 Warnings Error: top.DUT.dma_rd_master: DUT.rd_dts_slave (0x80000000..0x80001fff) overlaps emif_0.ctrl_amm_0 (0x0..0xffffffff) Error: top.mm_clock_crossing_bridge_0.m0: emif_0.ctrl_amm_0 (0x0..0xffffffff) is outside the master's address range (0x0..0xfffffff) Error: qsys-generate failed with exit code 3: 2 Errors, 5 Warnings is there an PCIe with external memory example in 21.3 format. don't tell me that I have to install a quartus version 17. Thanks, David Replies: Re: run AN708 on Quartus 21.3 Hi David, Thanks, With that said I am closing this thread. If you feel your support experience was less than a 9 or 10, please allow me to correct it before closing or please let me know the cause so that I may improve your future support experience. Great to work with you in this issue Regards, Wincent_Intel Replies: Re: run AN708 on Quartus 21.3 Hi David, This error is issued when the design capacity for the simulator is exceeded. See page-11 of https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20352.pdf 'Known Differences Between the Questa-Intel FPGA Edition and ModelSim* - Intel FPGA Edition' Few suggestions: 1) In Quartus -> Message tab, right click 'Message', select 'Suppress -> Suppress Message / Suppress Messages with Matching ID to suppress the message。 2) I found this KDB, it uses the "suppress" option along with vsim command ( vsim -suppress 10000) In your case, probably can try 'vsim -suppress 14408' instead of 'suppress = 14408' https://www.intel.com/content/www/us/en/support/programmable/articles/000074348.html Hope this help. Regards, Wincent_Intel Replies: Re: run AN708 on Quartus 21.3 Hi Wchiah I start a new struggle journey on AN829 and posted a challenge at a new thread. AN829 simulation ran but failed - Intel Communities hope you can have a look and give me some suggestion. this needs more detailed investigation into the example because I guess the problem is not just on the tool revision level. we can close this thread and thank you for all your help. David Replies: Re: run AN708 on Quartus 21.3 Wchiah, While I ran simulation of the AN829, I got this error message. # ** Error (suppressible): (vopt-14408) Intel Starter FPGA Edition recommended capacity is 5000 non-OEM instances. There are 9597 non OEM instances. Expect performance to be severely impacted. I guess this is because the free simulation tools provide by Intel does not support this complicate project, is that right? how to solve this problem if not pay the professional simulation tools? Thank you, David Replies: Re: run AN708 on Quartus 21.3 Hi Wchiah In fact, AN829 is what I am looking for, but the title didn't mention the DDR interface, so I didn't check in content. I think this time I do find somewhere to start with. Appreciate your help. have a good weekend David Replies: Re: run AN708 on Quartus 21.3 Hi David, If you have Stratix 10 , you can try to look at https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-guidance/pcie-support.html Gen3x8 Avalon -MM DMA with External DDR3/DDR4 Memory (AN 829) Other than that, you may check on Intel® FPGA Technical Training Catalog, It help me when I was a pioneer in FPGA area. https://www.intel.com/content/www/us/en/support/programmable/support-resources/fpga-training/catalog.html?s=Relevancy Also there is an Official Intel FPGA youtube channel which explain step to step function https://www.youtube.com/c/IntelFPGA For PCIe and DDR, you may refe to IP support center PCIE , https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-guidance/pcie-support.html EMIF , https://www.intel.com/content/www/us/en/support/programmable/support-resources/support-centers/emif-support.html Regards, Wincent_Intel Replies: Re: run AN708 on Quartus 21.3 Wchiah, Here is a little background of my project, I have an evaluation package from TI data acquisition chip AFE58JD48. the original system is 16 ADCs ( 8 lane of JESD204B, upstream is USB3). I need to use 64 ADCs ( 16 lane of JESD204B), USB3 is not fast enough, so I need to replace the USB3 module to PCIe3. the original design has interface from USB3 to DDR4 control, and I2C. if I have an example like AN708, I can learn how the PCIe interfaced with DDR. that will make it easier for me to integrate the PCIe interface into the system. besides AN708, any suggestion can make me go forward faster than start from the PCIe user guide will be appreciated. Thank you for help. David Replies: Re: run AN708 on Quartus 21.3 Hi David, I understand your frustration, but I would emphasize the support until version 17.0 is only specific Arria 10 AN708 design example. For PCIe IP, the latest version of Quartus do fully support all the way AVST, AVMM to PCIe DMA, and other PCIe design as well. Besides that, in the latest Agilex device, it support PCIe gen5 as well as some other useful design. The best I can help at the moment is help to submit an internal ticket to mention that there is a user who request an updated version for Arria 10 AN708 design example that supports latest Quartus version. Hope this help, let me know if anything else that you feel I can help more. Regards, Wincent_Intel Replies: Re: run AN708 on Quartus 21.3 Wchiah, If I view this from a different angle, the last update of the PCIe is version 17. which means that Intel gave up the support of the PCIe. I have heard many times that I should use 3rd party PCIe IP. I insisted to trust Intel to its IP. I am kind of understand what my friend's advice now. once it is possible, I should check a 3rd party IP. Thank you David Replies: Re: run AN708 on Quartus 21.3 Hi David, Is okay, I am happy if can help you. I believe you can be an expert somewhere in the future. Meanwhile, we can learn together at the moment, I also learn quite a lot from the question you ask right now. Thanks for actively reply and provide the needed information as well for us to further debug this. For example related to Arria 10 either PCIe or DMA, you may refer to Intel FPGA design store. https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/design-store.html?s=Relevancy&f:guidetm83741EA404664A899395C861EDA3D38B=%5BIntel%C2%AE%20Arria%C2%AE%5D Hope this answer your question, Regards, Wincent_Intel Replies: Re: run AN708 on Quartus 21.3 Hi Wchiah, Thank you very much for the investigation and a clear conclusion. it is very hard to get an ideal solution, but it is very critical to know what is going to happen, especially for a learner. I am not sure I would like to go to Quartus 17. I will spend more time to read ug_a10_pcie_avmm_dma-683425-666332. by the way, beside rely on AN708, is there other example with PCIe and DMA and DDR? the goal is to use PCIe in my application not AN708 itself. appreciate you time and patience. David Replies: Re: run AN708 on Quartus 21.3 Hi David, I did some investigation and determined that Quartus 17.0 onwards don't allow test bench generation with critical hard blocks not connected. The reference design attached in AN708 was generated using Quartus 17.0 only. This Quartus version allows test bench generation with hip_pipe and hip_control conduit exported. My suggestion at the moment will be please revert back to Quartus 17.0 to use QYS feature to generate the test bench system. To encounter this, I have opened an internal case to resolve this; so the AN708 simulation and test bench generation are also validated to allow migration. Hope the related team will work on this. Please accept my apologies for the frustration you have faced. Hope this is clarified. Regards, Wincent_Intel Replies: Re: run AN708 on Quartus 21.3 Hi Wchiah We are on the same page now. the project I uploaded can be compiled in Quartus 21.3. My question/problem was after open the top.sys at the platform designer. when generate testbench system. Error: can't read "intf_use_partner(pcie_rstn)": no such element in array Error: Error: can't read "intf_use_partner(pcie_rstn)": no such element in array Error: There were errors creating the testbench system. as a new user to PCIe and DDR system, I think the simulation environment will be very helpful to make deep understand of the interface. if the platform designer doesn't support to create the simulation environment automatically. is it possible to create a simulation for this PCIe and DDR example? How? Thank you very much David Replies: Re: run AN708 on Quartus 21.3 Hi David, I understand your feeling. That is why I am here to help you. I try the .qar file provided by you without modifying anything (just simple run full compilation) Using Quartus Pro Edition 21.3 . The design is able to compile without any error at all. Can you please try it again ? or on another laptop perhaps? Regards, Wincent_Intel Replies: Re: run AN708 on Quartus 21.3 I hope I remember it correctly. original this is 12. Replies: Re: run AN708 on Quartus 21.3 Hi Wchiah, This is my personal computer; I am the only user. I am using win10. it is very hard to understand why I don't have the right to access some file because I am the administrator. the more intelligent of the Windows software, the harder to understand how to use it, same as Quartus. appreciate your help. David Replies: Re: run AN708 on Quartus 21.3 Hi Wchiah, How to find the IP search path? how do I know which is unnecessary? by the way, can Intel provide a version of AN708 that can run with Quartus 21.3. I am learning generic PCIe IP by Intel example. I am not an Intel Platform expert. can I assume that there are not many people use Intel PCIe ip on latest quartus software. if it is not straight forward to me, hard to believe it is an easy job for other engineers. I really appreciate your help to solve this problem, should it be Intel's responsibility to provide a working example on the latest platform? is the latest release based on Quartus 17? Thank you, David Replies: Re: run AN708 on Quartus 21.3 Hi Dsun, Can you share with me which/where is 12bits value you are adjusting ? Maybe a printscreen ? I am interested to know the originally issue that might be causing the error so that I can further escalate this issue. Regards, Wincent_Intel Replies: Re: run AN708 on Quartus 21.3 Hi Dsun, Glad that the issue solve, are you using company workstation/computer ? Suspect some file access routes might be encrypted... For the new issue can you please r emove all the unnecessary custom IP paths mentioned in IP Search Path and try to generate testbench again ? Replies: Re: run AN708 on Quartus 21.3 I set the testbench output directory to C:/FPGA/aPcie/AN708_q170_projectCopy/top_tb/ why the tools want to update the files in the C:\intelFPGA_pro\21.3\ip\altera\altera_pcie\altera_pcie_hip_256_avmm\channelizer\example_design? Replies: Re: run AN708 on Quartus 21.3 good news, after I change the owner of the directory, the original error disappeared. bad news was that new errors appeared. Error: can't read "intf_use_partner(pcie_rstn)": no such element in array Error: Error: can't read "intf_use_partner(pcie_rstn)": no such element in array Error: There were errors creating the testbench system. Replies: Re: run AN708 on Quartus 21.3 by the way, could you duplicate the problem on your platform, if not, that means related to the tool installation. otherwise, is the project/software itself problem thanks, David Replies: Re: run AN708 on Quartus 21.3 I copied the project into a different directory, the software generates same error message. by the way, I can run other very complex simulation with Jesd204b and DDR4 with Nios2 core without any problem. I am learning PCIe now, don't know why I have this problem. Thank you for helping. David Replies: Re: run AN708 on Quartus 21.3 Yes, use platform designer. original package set to 12bit. the first time I choose 16 bits. there is a conflict of the base address. after I change it to 14 bits, it compiled. thank you, Replies: Re: run AN708 on Quartus 21.3 Hi David, Can I know where you change the CAS/RAS bits ? is it inside platform designer ? Hoping to hear back from you. Regards, Wincent_Intel Replies: Re: run AN708 on Quartus 21.3 Hi, Thanks for sharing with me. for the Error: Unexpected error writing the ensemble: java.io.FileNotFoundException: issue Normally You will receive the above mentioned error in the SOPC Builder if you have logged into a PC without admin priveleges and you try and generate one of the example designs that is located in the default installation. You can workaround this error by copying the example design from the installation directory into a new directory elsewhere on the PC. Can you please try it ? Regards Wincent_Intel Replies: Re: run AN708 on Quartus 21.3 Hi Wincent_Intel the Quartus was installed at C:\intelFPGA_pro\21.3 for the compilation, 1. did an IP auto update. 2. the new IP not support 12 bit CAS( or RAS I can't remember), first time I change it to 16 bits, then the error happens. after I change it to 14 bits. then it compile OK. Thank you, David Replies: Re: run AN708 on Quartus 21.3 Hi, Can you share with me how your resolved the compilation issue? For error "Error: Unexpected error writing the ensemble: java.io.FileNotFoundException:" Can you please check if The software was installed under Program Files folder ? If YES, I would suggest you to try unistalled Quartus Suite and installed again on root directory ( C:\Altera). Probably the problem was the space in the installation path ("Program Files"). Hope this help, Regards, Wincent_Intel Replies: Re: run AN708 on Quartus 21.3 Hi, Thank you for reaching out. Just to let you know that Intel has received your support request and I am assigned to work on it. Allow me some time to look into your issue. I shall come back to you with findings. Thank you for your patience. Best regards, Wincent_Intel Replies: Re: run AN708 on Quartus 21.3 Dear Intel friends, after some struggle, I can compile the projects. I have the following errors while I generate simulation example. could anyone give me some suggestion to solve the problem. Error: Unexpected error writing the ensemble: java.io.FileNotFoundException: C:\intelfpga_pro\21.3\ip\altera\altera_pcie\altera_pcie_hip_256_avmm\channelizer\example_design\top.qsys (Access is denied) Error: Unexpected error writing the ensemble: java.io.FileNotFoundException: C:\intelfpga_pro\21.3\ip\altera\altera_pcie\altera_pcie_hip_256_avmm\channelizer\example_design\sriov_mcdma_app_g3x8_256b.qsys (Access is denied) Error: Unexpected error writing the ensemble: java.io.FileNotFoundException: C:\intelfpga_pro\21.3\ip\altera\altera_pcie\altera_pcie_hip_256_avmm\channelizer\example_design\rddc_mc_256b.qsys (Access is denied) Error: Unexpected error writing the ensemble: java.io.FileNotFoundException: C:\intelfpga_pro\21.3\ip\altera\altera_pcie\altera_pcie_hip_256_avmm\channelizer\example_design\wrdc_mc_256b.qsys (Access is denied) Error: can't read "intf_use_partner(pcie_rstn)": no such element in array Error: Error: Unexpected error writing the ensemble: java.io.FileNotFoundException: C:\intelfpga_pro\21.3\ip\altera\altera_pcie\altera_pcie_hip_256_avmm\channelizer\example_design\top.qsys (Access is denied) Error: There were errors creating the testbench system. I attached the Quartus 21.3 compiled project, it can be compiled but not know anything else. Thank you, David - 2022-09-07