TSE GMII gmii_rx_dv without data_rx_valid signal - TSE GMII gmii_rx_dv without data_rx_valid signal Dear Community, I am using the Triple Speed Ethernet IP Core with the GMII interface on a board with a Cyclone 10GX220. The TSE MAC command register was initialised with: 0x2033 (SW Reset, Pad En, Promis En , RX En, TX En) When I send a UDP Broadcast packet from the PC to the board, the packet is visible on the GMII RX lines coming from PHY (see figure below). But data do not (or only sporadically) arrive on the Avalon-ST RX bus (see illustration) . What could be the reason for this? Fig. I have connected the TSE mac according to this illustration. The lan used has 1000Mbps. In the rare cases where the data received via GMII arrives on the Avalon-ST RX bus, it looks like this: This is it should always look like! Replies: Re: TSE GMII gmii_rx_dv without data_rx_valid signal Hi Zarquin, Thanks for confirming. I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you. Replies: Re: TSE GMII gmii_rx_dv without data_rx_valid signal Hi Pavee, yes, when the dialogue is closed, the TSE IP Core stops working. Regards Zarquin Replies: Re: TSE GMII gmii_rx_dv without data_rx_valid signal Hi Zarquin, I'm glad that you've found the rootcause. I just want to confirm with the dialogue box, so if you closed the dialogue box, TSE IP doesn't work as intended? Regards, pavee Replies: Re: TSE GMII gmii_rx_dv without data_rx_valid signal Wasn't a timing problem. It was a evaluation dialogue window problem: community.intel.com/t5/FPGA-Intellectual-Property/Triple-Speed-Ethernet-MII-GMII-Timing-Issue/m-p/1531419#M28109 Replies: Re: TSE GMII gmii_rx_dv without data_rx_valid signal In the meantime i think it is a timing problem. I will open a new post for this.