DQS Clock Buffer Location for QDR II and QDR II SRAM Controller with UniPHY and RLDRAM II Controller with UniPHY - DQS Clock Buffer Location for QDR II and QDR II SRAM Controller with UniPHY and RLDRAM II Controller with UniPHY Description The DQS clock buffer location for the UniPHY can cause hold time violations when placed suboptimally. The Quartus II software may suboptimally place the DQS clock buffer on a global or dual-regional clock after reentering the FPGA, so that it can be routed to the write side of the read capture FIFO buffer. Resolution Create a location assignment on the buffer to the same edge as the memory interface (for example EDGE_BOTTOM ). Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 10.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']