Why can I not accelerate my floating point division using the Floating Point Divider Custom Instruction - Why can I not accelerate my floating point division using the Floating Point Divider Custom Instruction Description There is currently a known issue where Nios® II Software Build tool for Eclipse (SBT4E) does not automatically add the "-mcustom-fpu-cfg=60-2" flag even if your design created with SOPC Builder or Qsys has a Floating Point Hardware Divider Custom Instruction. In this case, the floating point division instructions in your C program (e.g. float a,b,c; a=b/c;) will use the software floating point divider sub-routine instead of the floating point divider implemented in your hardware. In order to utilize the hardware divider, modify the "-mcustom-fpu-cfg" flag in the public.mk file in the BSP project generated by NiosII SBT4E from "-mcustom-fpu-cfg= 60-1 " to "-mcustom-fpu-cfg= 60-2 ". The compiler can then generate the desired custom instruction implementation by using the compiler flag. This issue will be fixed in a future release of Nios II SBT4E. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 9.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']