Rule C101: Gated clock should be implemented according to the Altera standard scheme - Rule C101: Gated clock should be implemented according to the Altera standard scheme Description You may see the following warning when running the Design Assistant tool in Quartus® II software on your compiled HPS design. Rule C101: Gated clock should be implemented according to the Altera standard scheme ; <hierarchy>:altdq_dqs2_inst|dqsbusout Resolution This warning is expected and can be safely ignored. Custom Fields values: ['novalue'] Troubleshooting 1408190367 False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 14.1 ['Arria® V GT FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA'] ['novalue'] ['novalue'] ['novalue']