Building a Generation 10 Transceiver PHY Layer - 37 Minutes In the Building a Generation 10 Transceiver PHY Layer course, you will learn how to configure the IP cores that make up an Arria® 10 transceiver PHY layer, namely the Arria® 10 Native PHY IP core, the transceiver PLL IP cores and the Transceiver PHY Reset Controller IP core. You will then learn how to properly connect the cores together to construct a custom transceiver PHY solution. Course Objectives At course completion, you will be able to: Configure the Arria® 10 transceiver PHY IP cores: 1) Arria® 10 Transceiver Native PHY IP core 2) Arria® 10 Transceiver ATX PLL IP, Arria® 10 FPLL or Arria® 10 Transceiver CMU PLL IP cores 3) Transceiver PHY Reset Controller IP core Construct an Arria® 10 transceiver custom PHY layer using the transceiver PHY IP cores Skills Required Familiarity with FPGA/CPLD design flow Familiarity with FPGA architecture Familiarity with the Quartus II design software Knowledge of Arria® 10 transceiver architecture Familiarity with high-speed interfaces and transmission protocols is helpful, but not required If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OG10XCVRPHY. FPGA_OG10XCVRPHY. <p>Building a Generation 10 Transceiver PHY Layer</p>