Can I route the Agilex™ 7 FPGA F-Series device out_refclk_fgt_[i] signal of the F-Tile Reference and System PLL Clocks FPGA IP to the FPGA core logic? - Can I route the Agilex™ 7 FPGA F-Series device out_refclk_fgt_[i] signal of the F-Tile Reference and System PLL Clocks FPGA IP to the FPGA core logic? Description No, you cannot route the Agilex™ 7 FPGA F-Series device out_refclk_fgt_[i] signal of the F-Tile Reference and System PLL Clocks FPGA IP to the FPGA core logic. Due to a problem in the Quartus® Prime Pro Edition Software version 24.3 and earlier, Quartus® Prime software will incorrectly compile designs that route the F-Tile Reference and System PLL Clocks FPGA IP out_refclk_fgt_[i] signal to the FPGA core logic. This signal is not intended for this purpose. Resolution To connect an Agilex™ 7 FPGA F-Series device reference clock to the FPGA core logic, you must use the out_coreclk_[i] port of the F-Tile Reference and System PLL Clocks FPGA IP. This problem will be fixed in a future version of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 14023928453 False ['F-Tile Reference and System PLL Clocks IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 24.4 ['Agilex™ 7 FPGA F-Series'] ['novalue'] ['novalue'] ['novalue']