How can I reduce the unexpectedly long synthesis time of a design which contains a very large shift register where the number of bits to be shifted is stored in another register? - How can I reduce the unexpectedly long synthesis time of a design which contains a very large shift register where the number of bits to be shifted is stored in another register? Description In the Quartus® Prime Standard Edition Software version 21.1 and earlier, if your design contains a very large shift register (1000's of bits wide) shifted by a shift operator, where the right operand of the shift operator is stored in a register, you might see that the compilation time of the design is unexpectedly long. Resolution To work around this problem in the Quartus® Prime Standard Edition Software, follow these steps: Replace the right operand of the shift operator with a data constant. Replace it with a case statement block. Use the original right operand as the judgment condition of the case statement, correspond to its different values, use the data constant as the right operand of the shift operator in different statements to shift the register. Additional Information The long compile time has been reduced in the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 15010455769 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Standard'] No plan to fix 17.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']