Why does the dual port ROM inference with read enable creates two RAM blocks instead of one when using Cyclone® IV FPGA device family? - Why does the dual port ROM inference with read enable creates two RAM blocks instead of one when using Cyclone® IV FPGA device family? Description You may see that there are 2 RAM blocks being implemented when inferring dual port ROM with the read enable. This is due to the Intel® Quartus® Prime Standard Edition Software code does not support read enable for dual ports ROM when using Cyclone® IV FPGA device family. Resolution To work around the problem, instantiate the On-Chip Memory Intel® FPGA IP to get a single RAM block. Custom Fields values: ['novalue'] Troubleshooting 15011962521 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Standard'] novalue 22.1 ['Cyclone® IV FPGAs'] ['novalue'] ['novalue'] ['novalue']