Why is the HDMI Intel® FPGA IP status flag SCDCS register bit 0 (clock_detected) always zero when read? - Why is the HDMI Intel® FPGA IP status flag SCDCS register bit 0 (clock_detected) always zero when read? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.3 of the HDMI Intel® FPGA IP, when reading status flag SCDCS register bit 0 (clock_detected) it will incorrectly return the value as 0. This problem only impacts designs that use the HDMI Intel® FPGA IP in TMDS mode. Resolution To work around this problem when using the Intel® Quartus® Prime Pro Edition Software version 21.3 of the HDMI Intel® FPGA IP, install patch 0.43. Download the patch Intel® Quartus® Prime Pro Edition version 21.3 Patch 0.43 for Windows (.exe) Download the patch Intel® Quartus® Prime Pro Edition version 21.3 Patch 0.43 for Linux (.run) Download the Readme for Intel® Quartus® Prime Pro Edition version 21.3 Patch 0.43 (.txt) This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 18022216568 False ['HDMI'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 22.3 21.3 ['Arria® 10 FPGAs and SoCs', 'Cyclone® 10 FPGAs', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']