Can I ignore the different clock domain setup timing violation inside Altera XAUI PHY IP? - Can I ignore the different clock domain setup timing violation inside Altera XAUI PHY IP? Description You can observe there are setup timing violations in below clock domain inside the Altera ® XAUI PHY IP. Launch clock: phy_mgmt_clk Latch clock: xaui_phy0|xaui_phy_plda_inst|xaui_phy|hxaui_0|use_device_family_siv_sv.hxaui_alt4gxb| hxaui_alt4gxb_alt4gxb_dksa_component|central_clk_div0|coreclkout The failing paths are due to one clock domain being synchronizing with another clock domain and there are 2 synchronizer registers for each failing path. Resolution To workaround this issue, you are safe to ignore the above different clock domain setup timing violation inside Altera XAUI PHY IP. This problem will be fixed in a future version of the Quartus® II software. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 11.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']