Error: alt_pr.avmm_slave (0x0..0x3f) is outside the master's address range (0x0..0x7) - Error: alt_pr.avmm_slave (0x0..0x3f) is outside the master's address range (0x0..0x7) Description You may see this error message when the Arria® 10 SX BSP board.sys file is opened in Qsys and you choose the option “Sync All System Infos” using Quartus® Prime software version 17.0 Resolution This problem will be fixed in a future version of the Quartus® Prime software versions. To work around this issue then change "Address width" of pipe_stage_alt_pr and clock_cross_host_alt_pr to 6. Move address of clock_cross_host_alt_pr.s0 to 0xcf00 or 0xcf40. If you recompile the base revision then this address change must also be reflected in the following file a10soc/arm32/driver/hw_mmd_constants.h by changing the ACL_PRCONTROLLER_OFFSET value to 0xcf40. Custom Fields values: ['novalue'] Troubleshooting FB: 482272; False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 17.1 17.0 ['Arria® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']