Is there any known issue with the table in Link X /Link X Top /Link X Location tab of the Agilex™ 5 FPGA MIPI D-PHY IP GUI? - Is there any known issue with the table in Link X /Link X Top /Link X Location tab of the Agilex™ 5 FPGA MIPI D-PHY IP GUI? Description Yes, in the Quartus® Prime Design Suite version 24.3 and prior, when selecting the desired Byte Location of the Link, the table (For didactical purposes, the example shows a 1 Clk & 4 Data links configuration) shown below may not reflect the entered byte location within the IO Bank. Resolution To ensure the entered byte location is correctly assigned, please verify that the table in the DPHY IP / IP Configuration tab's Enabled Links section shows the desired byte location for each enabled Link. This is fixed in the Quartus® Prime Design Suite version 25.1. Custom Fields values: ['novalue'] Troubleshooting 15013789768 False ['Interfaces'] ['FPGA Dev Tools Quartus® Prime Software'] 25.1 24.2 ['Agilex™ 5 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']