Why does the rready signal deassert when simulating High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 M-Series FPGA IP? - Why does the rready signal deassert when simulating High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 M-Series FPGA IP? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.4 and later, you might observe the AXI4 protocol violation at NOC input when the UNOC mode is enabled. Resolution This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 16018488105 False ['High Bandwidth Memory (HBM2E) Interface Agilex™ 7 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 22.4 ['Agilex™ 7 FPGA M-Series'] ['novalue'] ['novalue'] ['novalue']