Is there a known problem with Cyclone® III or Cyclone® IV devices if a user reset is deasserted before the device has entered user mode? - Is there a known problem with Cyclone® III or Cyclone® IV devices if a user reset is deasserted before the device has entered user mode? Description Due to a known problem with Cyclone® III and Cyclone® IV devices, unexpected register output behaviour might be caused when a user reset is deassserted before the device enters the user mode. Resolution To avoid this problem, Intel recommends that you deassert user logic reset after the device has entered user mode, or enable the clock source to your registered logic after the device has entered user mode. The INIT_DONE signal can be used to indicate that the device has entered the user mode. If the INIT_DONE signal is not enabled, refer to the tCD2UM ( CONF_DONE high to user mode) parameter in the device handbook. Custom Fields values: ['novalue'] Troubleshooting - False ['novalue'] ['novalue'] novalue novalue ['Cyclone® III FPGAs', 'Cyclone® III LS FPGA', 'Cyclone® IV E FPGA', 'Cyclone® IV GX FPGA'] ['novalue'] ['novalue'] ['novalue']