Why does the CDR fail to lock when using the F-Tile Ethernet FPGA Hard IP with the '200GE-4' variant in the Quartus® Prime Pro Edition Software version 23.2? - Why does the CDR fail to lock when using the F-Tile Ethernet FPGA Hard IP with the '200GE-4' variant in the Quartus® Prime Pro Edition Software version 23.2? Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.2, the CDR sometimes fails to lock to data signal when using the F-Tile Ethernet FPGA Hard IP with the "200GE-4" variant, and the PCS ready signal does not get asserted. During this release, the CDR Locked to Data signal fails to assert for the FGT lanes, even though the CDR Locked to Reference status is up. Resolution This problem has no workaround and fixed in the Quartus® Prime Pro Edition Software version 23.3. Custom Fields values: ['novalue'] Errata 18032117541 False ['F-Tile Ethernet Hard IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.3 23.2 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']