Why do output clocks of the IOPLL Intel® FPGA IP have incorrect phase shifts with respect to the reference clock in simulation in Intel Arria® 10 and Intel Cyclone® 10 GX? - Why do output clocks of the IOPLL Intel® FPGA IP have incorrect phase shifts with respect to the reference clock in simulation in Intel Arria® 10 and Intel Cyclone® 10 GX? Description Due to a problem with the simulation model generated by Intel® Quartus® Prime Software, output clocks of the IOPLL Intel FPGA IP may have incorrect phase shifts with respect to the reference clock in simulation in Intel Arria® 10 and Intel® Cyclone® 10 GX. The output clocks of the IOPLL Intel FPGA IP hardware have correct phase shifts according to the phase shift settings in the IP parameter editor. Resolution Perform hardware verification when checking phase shifts of output clocks of the IOPLL Intel FPGA IP in Intel® Arria® 10 and Intel® Cyclone® 10 GX. Custom Fields values: ['novalue'] Troubleshooting 1507477017, 2205908006 False ['IOPLL IP'] ['FPGA Dev Tools Quartus® Prime Software Pro', 'FPGA Dev Tools Quartus® Prime Software Standard'] No plan to fix 19.1 ['Arria® 10 FPGAs and SoCs', 'Cyclone® 10 FPGAs'] ['novalue'] ['novalue'] ['novalue']