Compilation Warnings for RapidIO IP Core 5.0 Gbaud Variations that Target an Arria V or Cyclone V Device - Compilation Warnings for RapidIO IP Core 5.0 Gbaud Variations that Target an Arria V or Cyclone V Device Description When you compile a 5.0 Gbaud RapidIO IP core variation that targets an Arria V or a Cyclone V device, the following warnings appear: Warning (332174): Ignored filter at rio.sdc(104): *rio*riophy_xcvr|clk_div_by_two could not be matched with a net Warning (332049): Ignored create_generated_clock at rio.sdc(104): Argument <targets> is an empty collection Info (332050): create_generated_clock -name clk_div_by_two_rio - source [get_nets *rio_rio_inst*pld8gtxclkout] -divide_by 2 [get_nets *rio*riophy_xcvr|clk_div_by_two] Warning (332174): Ignored filter at rio.sdc(167): clk_div_by_two_rio could not be matched with a clock Resolution This issue has no design impact. You can ignore these warnings. This issue is fixed in version 13.0 of the RapidIO MegaCore function. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 13.0 12.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']