The Nios® II Processor: Hardware Abstraction Layer - 34 Minutes This training will demystify the Nios II Hardware Abstraction Layer, or HAL. You will be introduced to the fundamental concepts of the Nios II HAL and see the various HAL resources that have been provided to accelerate software development for the Nios II processor. You will be introduced to the APIs available in the HAL, IO communication libraries, Newlib, and HAL BSP projects. You will also learn how to use interrupts with the Nios II process. This class provides a good base of knowledge for beginning to write your own drivers for the Nios II processor. Course Objectives At course completion, you will be able to: Describe the functionality and structure of a Nios II HAL API Name and Describe the major pieces of a HAL BSP project Write and register an interrupt service routine for the Nios II processor Interact with an IO peripheral using software functions from the HAL Skills Required Basic software development knowledge If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OEMB1150. FPGA_OEMB1150. <p>The Nios II Processor: Hardware Abstraction Layer</p>