Why does Intel® Quartus® Prime Standard/Pro software fail to pack coefficients into DSP Block when using FIR II IP core? - Why does Intel® Quartus® Prime Standard/Pro software fail to pack coefficients into DSP Block when using FIR II IP core? Description Due to a problem in the Intel® Quartus® Prime Standard/Pro Edition software version 17.1/18.0 and Intel® Quartus® Prime Standard Edition software version 18.1, the synthesis may not infer the use of DSP coefficients ROM correctly if you set AUTO_RAM_RECOGNITION and AUTO_ROM_RECOGNITION OFF. This results in low Fmax of FIR II IP core. Resolution To work around this problem in the Intel® Quartus® Prime Standard Edition software, follow the steps below. Set Assignments > settings > compiler settings > Advanced settings(Synthesis) > Auto RAM Replacement from OFF to ON. Set Assignments > settings > compiler settings > Advanced settings(Synthesis) > Auto ROM Replacement from OFF to ON. This Problem has been fixed in Intel® Quartus® Prime Pro Edition software version 18.1. Custom Fields values: ['novalue'] Troubleshooting 1507273746 False ['FIR II IP'] ['FPGA Dev Tools Quartus® Prime Software Pro', 'FPGA Dev Tools Quartus® Prime Software Standard'] 18.1 17.1 ['Arria® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']