Error (332000): ERROR: Argument "node_object" is an object filter that matches no objects. Specify one matches only one object - Error (332000): ERROR: Argument "node_object" is an object filter that matches no objects. Specify one matches only one object Description You may see the following error when trying to run <instance_name>_p0_pin_assignments.tcl file when implementing UniPHY based external memory interface IP generated in VHDL: Error (332000): ERROR: Argument <node_object> is an object filter that matches no objects. Specify one matches only one object. while executing "get_node_info -cell " (procedure "is_node_type_pll_clk" line 2) invoked from within "is_node_type_pll_clk " (procedure "get_input_clk_id" line 2) invoked from within "get_input_clk_id " (procedure "<instant_name>_p0_get_ddr_pins" line 240) invoked from within "<instant_name>_p0_get_ddr_pins allpins" (procedure "<instant_name>_p0_initialize_ddr_db" line 13) invoked from within "<instant_name>_p0_initialize_ddr_db <instant_name>_p0_ddr_db" invoked from within "if { ! [ info exists <instant_name>_p0_sdc_cache ] } { set <instant_name>_p0_sdc_cache 1 <instant_name>_p0_initialize_ddr_db <instant_name>_p0_ddr_db } else..." (file "../ddr3/<instant_name>/<instant_name>_p0.sdc" line 186) Resolution You need to modify the RTL code in the file <instant_name>_0002.v and make changes to signal declaration for the following signals, these signals are single bit in verilog code but are declared as std_logic_vector in VHDL wrapper for the IP: output wire [0:0] mem_ck, // .mem_ck output wire [0:0] mem_ck_n, // .mem_ck_n output wire [0:0] mem_cke, // .mem_cke output wire [0:0] mem_cs_n, // .mem_cs_n output wire [0:0] mem_ras_n, // .mem_ras_n output wire [0:0] mem_cas_n, // .mem_cas_n output wire [0:0] mem_we_n, // .mem_we_n by adding [0:0] you will match the signal declaration to be compatible with VHDL. This issue will be fixed in the future relase of Quartus II software. Related Articles Why does the VHDL wrapper file generated for DDR3 SDRAM Controller with UniPHY fail to compile in Quartus II software version 11.0? Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 11.1.2 ['Stratix® III FPGAs'] ['novalue'] ['novalue'] ['novalue']