JESD204B MegaCore IP Overview (Legacy Course) - 27 Minutes This online course will provide a broad overview of the JESD204B MegaCore® IP. In order to make sure that you understand all the terms and concepts used in the course, we begin with a discussion of the relevant portions of the JESD204B interface specification. Next, some of the important features of the JESD204B MegaCore IP are presented. Finally, data flow through the system is used to describe the functional details of the core. Course Objectives At course completion, you will be able to: Describe the features and functionality of the JESD204B MegaCore IP Skills Required Understanding of the JESD204B specification Familiarity with common high-speed transceiver architecture OR viewing the following course: "Transceiver Basics" Familiarity with FPGA/CPLD design flow Familiarity with the Quartus® Prime design software Some familiarity with Platform Designer If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OJESDOVERVIEW. FPGA_OJESDOVERVIEW. <p>JESD204B MegaCore IP Overview (Legacy Course)</p>