Why does the Intel® Stratix® 10 Single Port RAM show Don’t care value instead of Old data for read during write? - Why does the Intel® Stratix® 10 Single Port RAM show Don’t care value instead of Old data for read during write? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 17.1 and earlier, you will see incorrect behavior in simulation for read during write to an Intel® Stratix® 10 FPGA single-port RAM with the following parameters settings: altera_syncram_component.intended_device_family = "Stratix 10" altera_syncram_component.operation_mode = "SINGLE_PORT" altera_syncram_component.read_during_write_mode_port_a = "OLD_DATA" altera_syncram_component.ram_block_type = "M20K" This is only a simulation issue, you will not see this on hardware. Resolution To work around this problem, run the post-synthesis or post-fit netlist simulation instead of functional simulation. This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 18.1.1. Custom Fields values: ['novalue'] Troubleshooting 545719 551347 False ['RAM 1-PORT IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 18.1.1 17.1 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']