Internal Error: Sub-system: TIS_RC, File: /quartus/tsm/tis/tis_physical_timing_api.cpp, Line: 1334 - Internal Error: Sub-system: TIS_RC, File: /quartus/tsm/tis/tis_physical_timing_api.cpp, Line: 1334 Description During compilation of a design that targets an Arria V or Cyclone V device, compilation might fail with the error Internal Error: Sub-system: TIS_RC, File: /quartus/tsm/tis/tis_physical_timing_api.cpp, Line: 1334 This error might occur if your design has high M10K block usage. Resolution If your design contains LogicLock regions, allow the Fitter to place memory elements outside of their assigned LogicLock region by performing the following steps: In the LogicLock Regions window, right-click a LogicLock region, and then click Properties . In the Members list of the Properties dialog box, select design elements. Click Edit . The Edit Node dialog box opens. Under Excluded element types , click Edit . The Excluded Element Types dialog box opens. Under Excluded element types , turn on Memory . If your design does not contain LogicLock regions, or if allowing the Fitter to place memory elements outside of their assigned LogicLock regions fails to resolve the error, add the following line to the quartus.ini file for your project: fitter_rams_disallow_packed_mode = on Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 12.0.1 ['Arria® V FPGAs and SoCs', 'Cyclone® V FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']