Why does my VHDL variant of the eCPRI Intel® FPGA IP fail to simulate in Synopsys VCS MX®? - Why does my VHDL variant of the eCPRI Intel® FPGA IP fail to simulate in Synopsys VCS MX®? Description Due to a problem in the Intel® Quartus® Prime software versions 20.1 and later, when using a VHDL variant of the eCPRI Intel® FPGA IP in Synopsys VCS MX*, the simulator’s compiler will flag errors stating that there are type mismatches for parameter “ ADV_MAP ”. Resolution To work around this problem in the Intel® Quartus® Prime version 20.1 and later, follow the steps below: 1) Locate the generated top-level wrapper file of your eCPRI Intel® FPGA IP here: <variant_name>/sim 2) Change every “ ON ” or “ OFF ” string that is assigned to the parameter “ ADV_MAP ” to integer 1 or 0 , respectively, as shown below: From ADV_MAP : string := "ON"; To ADV_MAP : integer := 1; From ADV_MAP => "OFF", To ADV_MAP => 0, This problem is fixed starting with the Intel® Quartus® Prime software version 20.3. Custom Fields values: ['novalue'] Troubleshooting 1508309809 True ['Interfaces Communications CPRI (Primary)', 'Interfaces Communications CPRI (Primary)'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 20.3 20.1 ['Arria® 10 FPGAs and SoCs', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']