Signal Tap Logic Analyzer: Data Acquisition & Additional Features - 35 Minutes This training is part 4 of 4. The Signal Tap embedded logic analyzer (ELA) is a system-level debugging tool that monitors the state of internal FPGA design signals and triggers on custom, user-defined conditions during run-time operation of the device without having to bring signals out to device I/O pins. It integrates directly into your design, making it easy to perform functional debug. This final part of the training discusses how to run the logic analyzer to capture monitored signal data and how to analyze the captured data in a number of different formats. You'll also learn about many additional features of the tool, such as the creation and use of power-up triggers, advanced triggers, and how to easily expand tapped signal coverage through post-fit design simulation. Course Objectives At course completion, you will be able to: Run the logic analyzer and acquire monitored signal data Analyze the captured data in the Signal Tap file window or export to multiple file formats Make use of additional Signal Tap features such as power-up triggers and advanced triggers Tap and analyze additional signal nodes automatically through simulation Skills Required Basic knowledge of the Quartus Prime software knowledge of external logic Analyzer operations (optional) If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_ODSW1173. FPGA_ODSW1173. <p>Signal Tap Logic Analyzer: Data Acquisition & Additional Features</p>