Why does the FIR II Intel® FPGA IP use fewer DSP Blocks than the number shown in the resource estimation section of the IP GUI? - Why does the FIR II Intel® FPGA IP use fewer DSP Blocks than the number shown in the resource estimation section of the IP GUI? Description The string "Number of DSPs" under Resource Estimation in the FIR II Intel® FPGA IP GUI is inaccurate. It should be the "Number of 18 x 18 multipliers". This results in the Intel® Quartus® Prime Pro Edition Software Fitter reporting fewer DSP Blocks used than the estimation. Resolution No workaround is needed. This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 1508072315 False ['FIR II IP'] ['FPGA Dev Tools Quartus® Prime Software Pro', 'FPGA Dev Tools Quartus® Prime Software Standard'] 23.1 18.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']