How can we access the Intel® Stratix® 10 SoC SP Timer registers in UBOOT or Linux user space (EL0: non-privileged execution)? - How can we access the Intel® Stratix® 10 SoC SP Timer registers in UBOOT or Linux user space (EL0: non-privileged execution)? Description By default, the SP timers didn’t out of reset in UBOOT. We will fail to access the S10 SoC SP Timer registers in UBOOT or Linux user space(EL0:non-privileged execution). Resolution UBOOT changes made: /u-boot/arch/arm/mach-socfpga/spl_s10.c (added codes after line 70) socfpga_per_reset(SOCFPGA_RESET(SPTIMER0), 0); socfpga_per_reset(SOCFPGA_RESET(SPTIMER1), 0); /u-boot/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h (added codes after line 105) #define RSTMGR_SPTIMER0 RSTMGR_DEFINE(2, 6) #define RSTMGR_SPTIMER1 RSTMGR_DEFINE(2, 7) Then we can read/write the SP timers. SOCFPGA_STRATIX10 # mw ffd24800 ffffffff; mw ffd21160 01010101; mw ffd21164 01010101; mw ffd21064 01010101; mw ffd21068 01010101 SOCFPGA_STRATIX10 # stratix10swvp login: root Last login: Sat Jun 24 05:27:20 UTC 2017 on ttyS0 root@stratix10swvp:~# devmem2 0xffc03000 w 0xa5a5a5a5 root@stratix10swvp:~# devmem2 0xffc03000 Value at address 0xFFC03000 (0xffff8021c000): 0xA5A5A5A5 Custom Fields values: ['novalue'] Troubleshooting 492768 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 18.1.1 18.0.1 ['Stratix® 10 SX FPGA'] ['novalue'] ['novalue'] ['novalue']