Integrating an Analog to Digital Converter in Altera® MAX® 10 Devices - 24 Minutes This training is part 2 of 3. The Altera® MAX® 10 device family consists of Altera® FPGA's smallest, low-cost, instant-on programmable logic devices. Besides support for the Nios® II embedded soft processor and connections to high performance external memory, most Altera® MAX® 10 devices feature an integrated analog-to-digital converter (ADC) block. This part of the training discusses how to use the IP Parameter Editor to parameterize the ADC and how to integrate the generated IP into a design. Course Objectives At course completion, you will be able to: Understand the basic architecture and features of the analog to digital converter (ADC) IP found in Altera® MAX® 10 devices Implement the Altera® MAX® 10 ADC hard IP in an FPGA design Monitor analog inputs using the ADC Toolkit Skills Required Background in digital logic design Familiarity with the Altera® Quartus® Prime software Familiarity with the Platform Designer system design tool If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OMAXADC102. FPGA_OMAXADC102. <p>Integrating an Analog to Digital Converter in Altera MAX 10 Devices</p>