Why does the GTS Serial Lite IV IP design example fail VHDL simulation using the Riviera-PRO™ simulator? - Why does the GTS Serial Lite IV IP design example fail VHDL simulation using the Riviera-PRO™ simulator? Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.3, you will observe the GTS Serial Lite IV IP design example fail VHDL simulation using the Riviera-PRO simulator. Resolution To work around the above problem, you can apply either of the following methods: Perform Verilog simulation, or Use a different simulator. Custom Fields values: ['novalue'] Troubleshooting 15016748161 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 24.3 ['Agilex™ 5 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']