Why does my F-Tile Ethernet FPGA Hard IP Design Example cause an internal error when upgrading the design from the Quartus® Prime Pro Edition Software version 23.1 to version 23.2? - Why does my F-Tile Ethernet FPGA Hard IP Design Example cause an internal error when upgrading the design from the Quartus® Prime Pro Edition Software version 23.1 to version 23.2? Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.2, upgrading an F-Tile Ethernet FPGA Hard IP design example will cause an internal error when attempting to upgrade from version 23.1 if the design is targeted to the Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit (4x F-Tile). Resolution To work around this problem, generate a new clean Quartus® Prime Pro Edition Software version 23.2 design example from scratch using the same settings from your 23.1 design example. This problem has been fixed in version 23.3 of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 18031690566 False ['F-Tile Ethernet Hard IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.3 23.2 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']