System Connectivity Warning: qsys_top.clock_in.out_clk/iopll_0.refclk: iopll_0.refclk requires 125000000Hz, but source has frequency of 50000000Hz - System Connectivity Warning: qsys_top.clock_in.out_clk/iopll_0.refclk: iopll_0.refclk requires 125000000Hz, but source has frequency of 50000000Hz Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.4, you might see the warning above when viewing the Platform Designer system of the Agilex™ 7 FPGA - Nios® V/m Processor OCM to OCM. This is due to the Clock Bridge FPGA IP sourcing only 50MHz to the IOPLL FPGA IP and not the required 125MHz. Resolution To work around this problem in the Quartus® Prime Pro Edition Software version 23.4, set the Reference Clock Frequency for IOPLL FPGA IP to 50MHz. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 16022554925 False ['IOPLL IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.1 23.4 ['Agilex™ 7 FPGA F-Series'] ['novalue'] ['novalue'] ['Agilex™ 7 FPGA F-Series Dev Kit']