How can I use VSEC registers in my Hard IP for PCI Express? - How can I use VSEC registers in my Hard IP for PCI Express? Description The following is a framework for implementation of VSEC register usage. Resolution 1) Set up your VSEC memory in the FPGA fabric using Internal RAM. 2) In the Altera ® Vendor-Specific (VSEC) Extended Capability Header (offset 0x200), set bits [31:20] to 0x400 (reserved space for the HardIP, other reserved locations are also available) 3) Decode the TLPs that target the range 0x400 plus ( ) the size of memory needed for new VSEC capability 4) Ensure VSEC memory is decoded and encoded through application layer logic Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Arria® 10 GT FPGA', 'Arria® 10 GX FPGA', 'Arria® 10 SX FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']