Why do I see a Qsys width mismatch error when I connect pll_locked to transceiver reset controller? - Why do I see a Qsys width mismatch error when I connect pll_locked to transceiver reset controller? Description Due to a problem in the Quartus® II software version 14.0 and later, Qsys generates this error when you connect pll_locked to transceiver reset controller. This error affects designs that contain the JESD204B IP core. The width of pll_locked from the IP core is based per channel not per PLL. Resolution To work around this problem, create an adapter component with the following parameters to enable the connection in Qsys: * Adapter input pll_locked_from_jesd[1:0] * Adapter output pll_locked_from_jesd[1:0] with an output width of pll_locked_to_xcvr_rst_ctrl Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 14.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']