Why is there higher than expected FPGA resource utilization when instantiating the RAM: 2-Port Intel® FPGA IP with the Emulated TDP dual clock mode parameter enabled? - Why is there higher than expected FPGA resource utilization when instantiating the RAM: 2-Port Intel® FPGA IP with the Emulated TDP dual clock mode parameter enabled? Description When a RAM: 2-Port Intel® FPGA IP with the Emulated TDP dual clock mode parameter enabled is instantiated in the Intel® Quartus® Prime Software, you might see a higher-than-expected FPGA resource utilization when targeting Intel® Stratix® 10 devices. This is caused by the additional FIFOs implemented by the RAM: 2-Port Intel® FPGA IP. Resolution To work around this problem, perform the following steps: Navigate through the hierarchy and find the fifo_wrapper_in instance. Move on through the hierarchy until you come across the dcfifo_component instance. Reduce the value of the LPM_NUMWORDS and LPM_WIDTHU parameters . The value assigned for LPM_NUMWORDS must comply with the following equation: 2^LPM_WIDTHU. Make sure the FIFO depth is appropriate to support the data rate of your design. As an example: dcfifo_component.lpm_numwords = 16 dcfifo_component.lpm_widthu = 4 Repeat steps 1 to 3 for the fifo_wrapper_out instance . Custom Fields values: ['novalue'] Troubleshooting 2205689125 False ['RAM 2-PORT IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 17.1 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']