Why do I see timing constraint problems with the tx_clkout and pipe_hclk output clocks in Intel® Arria® 10 PIPE designs? - Why do I see timing constraint problems with the tx_clkout and pipe_hclk output clocks in Intel® Arria® 10 PIPE designs? Description The tx_clkout and pipe_hclk output clocks are incorrectly constrained in the PIPE designs in the Quartus® II Software version 14.0 Intel® Arria® 10 Edition. Resolution To fix this problem, in your top level Synopsys Design Constraints (.SDC) file, follow these steps: Include the derive_pll_clock constraint in your SDC file. In a line beneath the derive_pll_clock constraint, use the remove_clock constraint to remove tx_clkout and pipe_hclk. Recreate these clocks at their interfaces using the create_clock SDC command Custom Fields values: ['novalue'] Troubleshooting 2205864850 False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 14.0a10 ['Arria® 10 GT FPGA', 'Arria® 10 GX FPGA', 'Arria® 10 SX FPGA'] ['novalue'] ['novalue'] ['novalue']