Why am I observing failures to read base Channel 0 in a multi-lane design for the GTS Serial Lite IV IP? - Why am I observing failures to read base Channel 0 in a multi-lane design for the GTS Serial Lite IV IP? Description Due to a problem in the Avalon® Memory-Mapped (AVMM) decoder, for a multi-lane GTS serial lite IV IP design, if you perform read transactions on channel N first, then read base channel 0, you might observe that the AVMM interface will hang. Single-lane designs and write transactions are not affected. However, this may affect the configuration of internal loopback mode. Resolution There is no workaround available. You are recommended not to initiate read transaction on channel 0 after reading channel N. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 15017686740 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 25.1 ['Agilex™ 5 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']