MAX® 10 FPGA Developer Center - The FPGA Developer Center is organized into industry-standard stages, which provides you with various resources to complete your FPGA design. Each design step is detailed in the expandable sub-sections with links that allow you to select and move between the various Generation 10 device series. Find more information about MAX 10 FPGA resources to help complete your design with device information, interface protocols, design planning, and more. Design Pages {"title":"MAX® 10 FPGA Developer Center"} Documentation 1. Device Information User Guides / Device Overview / Device Datasheet / Application Notes MAX® 10 FPGA Device Datasheet MAX® 10 Clocking and PLL User Guide MAX® 10 Analog to Digital Converter User Guide MAX® 10 FPGA Device Overview MAX® 10 General Purpose I/O User Guide MAX® 10 High-Speed LVDS I/O User Guide MAX® 10 FPGA Configuration User Guide MAX® 10 Power Management User Guide MAX® 10 Embedded Memory User Guide MAX® 10 FPGA Device Architecture MAX® 10 User Flash Memory User Guide MAX® 10 FPGA Signal Integrity Design Guidelines MAX® 10 FPGA Device Family Pin Connection Guidelines MAX® 10 FPGA Design Guidelines FPGA Parallel Flash Loader IP Core User Guide FPGAs Remote Update IP Core User Guide AN 286: Implementing LED Drivers in Altera MAX® Series AN 773: Drive-On-Chip Reference Design for MAX® 10 Devices AN 100: In-System Programmability Guidelines AN 265: Using Altera MAX® Series as Microcontroller I/O Expanders AN 294: Crosspoint Switch Matrices in Altera MAX® Series AN 425: Using the Command-Line Jam STAPL Solution for Device Programming AN 447: Interfacing FPGA Devices with 3.3/3.0/2.5 V LVTTL/LVCMOS I/O Systems AN 486: SPI to I2C Using Altera MAX® Series AN 488: Stepper Motor Controller Using Altera MAX® Series AN 490: Altera MAX® Series as Voltage Level Shifters AN 491: Power Sequence Auto Start Using Altera MAX® Series AN 492: CF+ Interface Using Altera MAX® Series AN 493: I2C Battery Gauge Interface Using Altera MAX® Series AN 494: GPIO Pin Expansion Using I2C Bus Interface in Altera MAX® Series AN 495: IDE/ATA Controller Using Altera MAX® Series AN 496: Using the Internal Oscillator IP Core AN 498: LED Blink Using Power Sequencing in Altera MAX® Series AN 500: NAND Flash Memory Interface with Altera MAX® Series AN 501: Pulse Width Modulation Using Altera MAX® Series AN 502: Implementing SMBus Controller in Altera MAX® Series AN 509: Multiplexing SDIO Devices Using Altera MAX® Series AN 522: Implementing Bus LVDS Interface in Supported FPGA Device Families AN 630: Real-Time ISP and ISP Clamp for FPGAs MAX® Series AN 631: Replacing Serial EEPROMs with User Flash Memory in FPGAs MAX® Series AN 741: Remote System Upgrade for MAX® 10 FPGA Devices over UART with the Nios® II Processor AN 752: Guidelines for Handling Altera Wafer Level Chip Scale Package (WLCSP) AN 370: Using the FPGA Serial Flash Loader with the Quartus® Prime Software Design Examples MAX® 10 FPGA Design Examples on Design Store Training and Videos Integrating an Analog to Digital Converter in Altera® MAX® 10 Devices Introduction to Analog to Digital Conversion in Altera® MAX® 10 Devices Remote System Upgrade in Altera® MAX® 10 Devices Using the ADC Toolkit in Altera® MAX® 10 Devices Using the MAX® 10 User Flash Memory with the Nios® II Processor Using the MAX® 10 User Flash Memory MAX® 10 FPGA Videos Development Kits MAX® 10 FPGA Development Kit User Guide MAX® 10 FPGA 10M50 Evaluation Kit User Guide MAX® 10 FPGA (10M08S, 144-EQFP) Evaluation Kit User Guide Documentation 2. Interface Protocols User Guides / Device Overview / Device Datasheet External Memory Interface MAX® 10 External Memory Interface User Guide External Memory Interfaces IP Support Center User Guides / Application Notes Ethernet FPGA Triple-Speed Ethernet IP Core User Guide User Guides DSP LDPC IP Core User Guide ALTERA_CORDIC IP Core User Guide BCH IP Core User Guide FFT IP Core User Guide FIR II IP Core User Guide Viterbi IP Core User Guide Turbo IP Core User Guide High-Speed Reed-Solomon IP Core User Guide Reed-Solomon II IP Core User Guide NCO IP Core User Guide Random Number Generator IP Core User Guide User Guides Embedded Embedded Peripherals IP User Guide Design Examples Version DDR3 SDRAM with Board Test System Console 16.0 MAX® 10 DDR3 Design with Debug Feature 16.0 Release Notes IP Release Notes Training and Videos Guide for New External Memory Interface (EMIF) Spec Estimator Documentation 3. Design Planning User Guides / Device Overview / Device Datasheet Platform Designer User Guide DSP Builder for FPGAs MAX® 10 FPGA Design Guidelines Training and Videos Fast & Easy I/O System Design with Interface Planner Documentation The Quartus® Prime Pro Edition software offers a mature synthesizer that allows you to enter your designs with maximum flexibility. If you are new to these languages, you can use online examples or built-in templates to get you started. The Quartus® Prime Pro Edition software offers Verilog and VHDL templates of frequently used structures. For more information on using these templates, refer to the "Using Provided HDL Templates" section of the Quartus® Prime Pro Handbook. 4. Design Entry User Guides / Device Overview / Device Datasheet / White Paper Quartus® Prime Standard Edition Handbook Volume 1 Design and Synthesis Advanced Synthesis Cookbook Applying the Benefits of Network on a Chip Architecture to FPGA System Design Design Examples Platform Designer Tutorial Design Example Training and Videos Using the Altera® Quartus® Prime Standard Edition Software: An Introduction Introduction to Verilog HDL Verilog HDL Basics Verilog HDL Advanced SystemVerilog with Quartus® Prime Design Software VHDL Basics Introduction to Platform Designer Platform Designer in the Altera® Quartus® Prime Pro Edition Software Creating a System Design with Platform Designer: Getting Started Using the Altera® Quartus Prime Pro Edition Synthesis Engine Software Downloads Download center for all versions of the Quartus® Prime software Documentation 5. Simulation and Verification User Guides / Device Overview / Device Datasheet / Application Notes Quartus® Prime Standard Edition User Guide: Third-party Simulation Simulation Quick-Start for ModelSim-Altera® FPGA Edition Simulating the a8237 Model with the Visual IP Software Avalon® Verification IP Suite User Guide Altera® FPGA Software Installation and Licensing Simulating the a8251 Model with the Visual IP Software Simulating the a8259 Model with the Visual IP Software Simulating the Reed-Solomon Model with the Visual IP Software Simulating the Turbo Encoder/Decoder Model with the Visual IP Software AN 720: Simulating the ASMI Block in Your Design AN 351: Simulating Nios® II Processor Designs AN 585: Simulation Debugging Using Triple Speed Ethernet Testbench Simulating FPGAs Devices with IBIS Models Simulating FPGA Designs Design Examples Avalon Verification IP Suite Design Example Training and Videos Advanced System Design Using Platform Designer: System Verification with System Console Advanced System Design Using Platform Designer: Component & System Simulation Software Downloads FPGA Development Tools Quartus® Software Documentation 6. Implementation and Optimization User Guides / Device Overview / Device Datasheet Quartus® Prime Pro and Standard Software User Guides MAX® CPLDs and FPGAs Training and Videos Beginner Workshop for Altera® FPGAs The Altera® Quartus® Prime Software: Foundation (Standard Edition) (Online Training) Documentation 7. Timing Analysis User Guides / Device Overview / Device Datasheet / Application Notes Timing Analysis Overview Quartus® II Scripting Reference Manual SDC and TimeQuest API Reference Manual Quartus® Prime Timing Analyzer Cookbook AN 366: Understanding I/O Output Timing for FPGAs Devices AN 471: High-Performance FPGA PLL Analysis with TimeQuest AN 433: Constraining and Analyzing Source-Synchronous Interfaces AN 775: I/O Timing Information Generation Guidelines Design Examples Timing Analyzer Design Examples Training and Videos Getting Started with the TimeQuest Timing Analyzer Quartus® Prime Pro Software Timing Analysis – Part 1: Timing Analyzer Quartus® Prime Pro Software Timing Analysis – Part 2: SDC Collections Quartus® Prime Pro Software Timing Analysis – Part 3: Clock Constraints Quartus® Prime Pro Software Timing Analysis – Part 4: I/O Interfaces Quartus® Prime Pro Software Timing Analysis – Part 5: Timing Exceptions Timing Analysis: Lecture Timing Analysis: Hands-on Labs FPGA Timing Closure: Lecture FPGA Timing Closure: Hands-On Lab Documentation 8. On-Chip Debug User Guides / Device Overview / Device Datasheet / Application Notes Analyzing and Debugging Designs with System Console FPGAs Virtual JTAG (FPGAs_virtual_jtag) IP Core User Guide FPGA-Adaptive Software Debug and Performance Analysis System Trace Macrocell Packs Major Benefits for High-Performance SoC System Debug FPGA USB Download Cable User Guide FPGA Download Cable II User Guide EthernetBlaster Communications Cable User Guide BSDL Support AN 827: Unified Tool for Generating Programming Files AN 323: Using SignalTap II Embedded Logic Analyzers in SOPC Builder Systems, Design files AN 446: Debugging Nios® II Systems with the SignalTap II Logic Analyzer AN 693: Remote Hardware Debugging over TCP/IP for FPGAs SoC AN 541: SerialLite II Hardware Debugging Guide AN 543: Debugging Nios® II Software Using the Lauterbach Debugger AN 585: Simulation Debugging Using Triple Speed Ethernet Testbench AN 624: Debugging with System Console over TCP/IP Training and Videos Debugging JTAG Chain Integrity On-Chip Debugging of Memory Interfaces IP in Altera® FPGA Devices FPGA Wiki Development Boards and Kits Software Downloads Quartus® Prime Software FPGA Licensing Support Center Licensing Questions and Answers Cable and Adapter Drivers Information Operating System (OS) Support Knowledge Base Solution Search the Knowledge Base for MAX® 10 Devices For additional information, search the following resources: Documentation , Training Courses , Videos , Design Examples , and Knowledge Base . Explore Other Developer Centers For other design guidelines, visit the following Developer Centers: