Why do I see the warning message "Ignored filter at file.sdc(line): CLK could not be matched with a clock"? - Why do I see the warning message "Ignored filter at file.sdc(line): CLK could not be matched with a clock"? Description In the Quartus® Prime Standard Edition Software version 23.1 and earlier, you might see some constraints targeting a user-created clock ignored by the Timing Analyzer. Resolution To avoid this problem, make sure the clock declaration constraint does not include any additional spaces in the -name argument. When there are additional spaces, they are included as part of the clock name. For example: The constraint create_clock -name {clk } -period 10 [get_ports clk100] should be modified to create_clock -name {clk} -period 10 [get_ports clk100]. Custom Fields values: ['novalue'] Troubleshooting 15014076843 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Standard'] No plan to fix 23.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']