Can the Intel® Max® 10 Dual Configuration Intel FPGA IP Core trigger read operation from multiple registers in one operation from offset 2? - Can the Intel® Max® 10 Dual Configuration Intel FPGA IP Core trigger read operation from multiple registers in one operation from offset 2? Description Yes. In the Intel® Max® 10 Dual Configuration Intel FPGA IP Core, you need to trigger the desired operation from offset 2 before any read operation of offset 4, 5, 6, and 7. Offset 2 has 4 bits to trigger read operation from 4 registers. These bits are not one-hot. So you can enable multiple bits in offset 2 to trigger read operations from multiple registers. Please note that the time until ubusy de-assertion after offset 2 operation becomes longer as the number of registers to be read increases. Resolution Refer to table 36 in Intel® MAX® 10 FPGA Configuration User Guide . Custom Fields values: ['novalue'] Troubleshooting 1507132351 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 19.3 18.1 ['MAX® 10 10 FPGAs'] ['novalue'] ['novalue'] ['novalue']