Why does compilation report in the Quartus® Prime Pro Edition Software not showing PLL Freq Min Lock and PLL Freq Max Lock? - Why does compilation report in the Quartus® Prime Pro Edition Software not showing PLL Freq Min Lock and PLL Freq Max Lock? Description In the Quartus® Prime Pro Edition Software, the PLL Freq Min Lock, PLL Freq Max Lock reports for IOPLL, and Fractional PLL (fPLL) are removed from the compilation report for the following device family: Agilex™ FPGA Stratix® 10 FPGA Arria® 10 FPGA Cyclone® 10 GX FPGA Resolution This problem is fixed in Quartus® Prime Pro Edition Software Custom Fields values: ['novalue'] Troubleshooting 1507184970 False ['IOPLL IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 19.3 17.1 ['Agilex™ 7 FPGAs and SoCs', 'Arria® 10 FPGAs and SoCs', 'Cyclone® 10 GX FPGA', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']