Internal Error: Sub-system: ASMGX, File: /quartus/comp/asmgx/asmgx_arriav.cpp, Line: 575 Illegal setting: (side, triplet, channel) = (1,1,1): (iqtxrxclk_a_sel, iqtxrxclk_b_sel) =(4,1) - Internal Error: Sub-system: ASMGX, File: /quartus/comp/asmgx/asmgx_arriav.cpp, Line: 575 Illegal setting: (side, triplet, channel) = (1,1,1): (iqtxrxclk_a_sel, iqtxrxclk_b_sel) =(4,1) Description Due to a problem in the Quartus® II software, you may see this error when compiling an Arria® V design using Transceivers. This is the result of TX or RX clock routing congestion. Resolution To work around this problem, try using the txclkout and rxclkout ports from a different channel to alleviate the congestion. Custom Fields values: ['novalue'] Troubleshooting 1408038563 False ['novalue'] ['FPGA Dev Tools Quartus II Software'] No plan to fix 13.1 ['Arria® V FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']