10316 VHDL error, character "0" used but not declared for type "std_logic_vector" - 10316 VHDL error, character "0" used but not declared for type "std_logic_vector" Good morning everyone, you have helped me before and I am very grateful for that. Now I come with another doubt, this time it has to do with the code: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; entity alu is port ( s:in std_logic_vector (2 downto 0); a:in std_logic_vector (3 downto 0); b:in std_logic_vector (3 downto 0); f:out std_logic_vector (3 downto 0) ); end alu; architecture comportamiento of alu is begin with s select f<= a+b when "000", a-b when "001", a or b when "011", a xor b when "100", a and b when "101", 0 when others; end comportamiento; The error it throws is: 10316 VHDL error at alu.vhd(25): character "0" used but not declared for type "std_logic_vector" I don't understand why if it is declared "std_logic_vector". I appreciate your help. Replies: Re: 10316 VHDL error, character "0" used but not declared for type "std_logic_vector" Assuming line 25 is "0 when others", since f is a std_logic_vector, this should be: "000" when others; Single bit values would be enclosed by ' (like '0') but multi-bit should be double-quotes ("000").