Why do I receive a static CRC value and an incorrect video pixel data input at the CRC modules when using the DisplayPort Intel® FPGA IP? - Why do I receive a static CRC value and an incorrect video pixel data input at the CRC modules when using the DisplayPort Intel® FPGA IP? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.2, the DisplayPort Intel® FPGA IP, the DisplayPort TX, and RX CRCs have the following errors: Incorrect and static CRC value when the DisplayPort Intel® FPGA IP is configured to 1 or 2 PIXELS_PER_CLOCK at HBR data rates. Incorrect video pixel data input of the CRC modules when the DisplayPort intel® FPGA IP is configured to 2 or 4 PIXELS_PER_CLOCK at HBR data rates. #Note: HBR data rates are referring to all DP1.4 data rates including RBR, HBR, HBR2 and HBR3. Resolution This problem has been fixed starting in the Intel® Quartus® Prime Pro Edition Software version 22.4. Custom Fields values: ['novalue'] Troubleshooting 15012246314 False ['DisplayPort'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 22.4 22.2 ['Agilex™ 7 FPGAs and SoCs', 'Arria® 10 FPGAs and SoCs', 'Cyclone® 10 FPGAs', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']