Why do the Arria® V GZ and Stratix® V Hard IP for PCI Express exit hot reset early? - Why do the Arria® V GZ and Stratix® V Hard IP for PCI Express exit hot reset early? Description The Arria® V GZ and Stratix® V Hard IP for PCI Express® exit the LTSSM state Hot Reset immediately when the soft reset controller is being used. This causes the Hard IP to exit the hot reset state before the connected Root Port. No impact has been observed in real hardware. Resolution This problem is fixed starting with the Intel® Quartus® Prime Standard Edition Software version 14.0. Custom Fields values: ['novalue'] Troubleshooting 1408045082 False ['Arria® V GZ Hard IP for PCI Express IP'] ['FPGA Dev Tools Quartus II Software'] 14.0 13.1 ['Arria® V GZ FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']