Why cant I turn on the rx_clklow and rx_fref ports in the Transceiver Native PHY IP Core for of Arria V, Cyclone V, and Stratix V devices? - Why cant I turn on the rx_clklow and rx_fref ports in the Transceiver Native PHY IP Core for of Arria V, Cyclone V, and Stratix V devices? Description Due to a problem with the Altera Transceiver PHY IP Core User Guide (PDF), the rx_clklow and rx_fref ports are incorrectly listed as available on the Native PHY IP Core for Arria ® V, Cyclone ® V and Stratix ® V devices. Resolution This problem will be fixed in a future version of the Altera Transceiver PHY IP Core User Guide (PDF). Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']